This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2003-120098, filed Apr. 24, 2003, the entire contents of which are incorporated herein by reference.
1. Field of the Invention
This invention relates to a semiconductor integrated circuit device and a method of manufacturing the same, and more particularly, it relates to a semiconductor integrated circuit device incorporating a DRAM in which a memory cell transistor and a logic transistor are integrated on the same semiconductor substrate, and a method of manufacturing the same.
2. Description of the Related Art
Generally in a semiconductor integrated circuit device incorporating a DRAM, metal silicide is formed on a gate electrode by a self-aligned silicidation process. It is thus impossible to form a cap insulating film such as a silicon nitride film on the gate electrode, giving a disadvantage that a self-aligned contact cannot be used which forms a contact self-aligningly with the gate electrode of a memory cell transistor.
Therefore, as has been conventionally known, for example, Jpn. Pat. Appln. KOKAI Publication No. 2000-232076 describes a semiconductor integrated circuit device incorporating a DRAM wherein metal silicide is formed respectively on source and drain regions and on the gate electrode of a logic transistor, and on the gate electrode of the memory cell transistor so as to achieve high-speed operation, and a sidewall insulating film is formed between the memory cell transistors so as to form a self-aligned contact with the gate electrode of the memory cell transistor.
However, gate processing is carried out individually for the memory cell transistor and logic transistor in the one described in the above document, which leads to a disadvantage of complicated manufacturing processes.
It is therefore desired that metal silicide is formed respectively on the source and drain regions and on the gate electrode of the logic transistor, and on the gate electrode of the memory cell transistor so as to achieve high-speed operation, and that the self-aligned contact can be formed with the gate electrode of the memory cell transistor, and further that the gate processing is carried out simultaneously for the logic transistor and memory cell transistor to reduce the number of manufacturing processes.
According to one aspect of the present invention, there is provided a method of manufacturing a semiconductor integrated circuit device comprises: sequentially forming a gate insulating film, a conductor film containing silicon, and a cap insulating film containing a member capable of selectively etching a silicon nitride film in each of a first silicon semiconductor region and a second silicon semiconductor region; patterning a laminated film constituted of the cap insulating film and the conductor film to form a gate electrode in each of the first and second silicon semiconductor regions; using the laminated film as a mask for introducing impurity to selectively introduce the impurity so as to form source and drain diffusion regions in each of the first and second silicon semiconductor regions; forming a first silicon nitride film on a sidewall of each of the laminated films; forming a second silicon nitride film on an entire surface; depositing a first insulating film on the entire surface, and then leaving the first insulating film between the gate electrodes in the first silicon semiconductor region; depositing a second insulating film in the second silicon semiconductor region, and then leaving the second insulating film on a sidewall of each of the laminated films in the second silicon semiconductor region; removing the second silicon nitride film on each of the laminated films and the second silicon nitride film left on a surface of the second silicon semiconductor region; removing the cap insulating film left above each of the gate electrodes; forming a metal silicide film on a surface of the conductor film of each of the gate electrodes and forming a metal silicide film on each surface of the source and drain diffusion regions formed in the second silicon semiconductor region; and depositing a third silicon nitride film on the entire surface, and then leaving the third silicon nitride film on each of the gate electrodes.
According to another aspect of the present invention, there is provided a semiconductor integrated circuit device comprises: a pair of first gate electrodes including a conductor film which are each provided via a gate insulating film in a first silicon semiconductor region; a first diffusion region provided in the first silicon semiconductor region between the pair of first gate electrodes; first metal silicide films provided on upper surfaces of the pair of first gate electrodes respectively; first silicon nitride films provided on the pair of first gate electrodes respectively; second silicon nitride films provided respectively on sidewalls of a laminated film constituted of the pair of first gate electrodes and the first silicon nitride films; a third silicon nitride film provided on the second silicon nitride film so that the first diffusion region is exposed in a flat portion positioned between the pair of first gate electrodes; a self-aligned contact provided between the pair of first gate electrodes and electrically connected to the diffusion region; a second gate electrode including a conductor film which is formed in a second silicon semiconductor region via a gate insulating film; a pair of second diffusion regions formed in the second silicon semiconductor region positioned on both surfaces of the second gate electrode; a second metal silicide film formed on an upper surface of the second gate electrode; a fourth silicon nitride film provided on the second gate electrode; a fifth silicon nitride film provided on a sidewall of a laminated film constituted of the second gate electrode and the fourth silicon nitride film; a sixth silicon nitride film provided on the fifth silicon nitride film so as to extend onto a portion of the surface of the pair of second diffusion regions; third metal silicide films provided respectively on the surfaces of the pair of second diffusion regions which are not covered with the sixth silicon nitride film; an insulating film provided on the sixth silicon nitride film; and a seventh silicon nitride film provided on the insulating film.